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Как отремонтировать хеш-плату Antminer S9K S9SE?

Antminer S9K S9SE Hash Board Repair Guide

Version date: 2022.7.ix

File Category: Maintenance Plan

Content of this Volume: It mainly describes the troubleshooting of various faults of S9K S9SE, and how to use the test tool for accurate positioning.

※ The copyright of this article belongs to Bitmaintech Pte.Ltd. (Bitmain). The article shall solely exist reprinted, extracted or used in whatever other ways with the permission of the copyright owner. Please contact Bitmain official customer service if at that place is any demand of reprinting or quoting.

I. Requirements on the Maintenance Platform

1. The constant temperature soldering iron (350-400°C). The tip soldering fe caput is used for soldering chip resistors and capacitors.

2. The thermal chimney is used for bit disassembly and soldering, be careful not to heat for a long fourth dimension to avoid PCB foaming.

3. APW3++ power supply (output 12V, 133A Max), used for exam and measurement of the hash lath.

iv.The Fluke 15b+ multimeter, tweezers, S9k S9se test jig (if there is condition, an oscilloscope can exist configured).

5. Flux, water for cleaning panel with anhydrous alcohol; water for cleaning console is used to clean flux residue and appearance after maintenance.

6. Thermally conductive adhesive is used to re-attach the cooling fin after repair.

If you need to repair Antminer S9k S9se, in addition to the necessary tools mentioned above, you likewise need Universal test fixture, 862D desoldering station, Tin can scraper and other efficient tools.

Of course, this choice may be more troublesome, you can besides choose the convenient Bitmain Antminer hash board repair bundle.

II. Requirements on Maintenance Operations

1. The maintenance personnel must accept certain electronic knowledge, more than one yr of maintenance feel, and master QFN bundle welding technology.

2. After repair, the hash board must be tested twice and confirmed as OK before information technology can pass!

3. Pay attending to the operation method when replacing the chip. After replacing whatsoever accessories, the PCB board is not plain deformed, and the replaced parts and the surrounding surface area shall be checked for whether there is open and brusk circuit.

4. Determine the maintenance station object and the corresponding test software parameters and examination jigs.

five. Check whether the tools and jigs can work commonly.

(Whether the power output is the same as the setting in the jig config file. Unlike BIN level and flake bundle style need to correspond to the config and single-board-test files of the single board examination jig program.)

3. Principle and Structure

ane. Principle overview

ane.1 S9K S9SE hash board is composed of 6 voltage domains continued in series. There are 10 BM1393 chips in each voltage domain, and in that location are 60 BM1393 chips on the whole board.

one.ii At that place are 208 cores on a single BM1393 chip, the domain voltage is 1.6V, and the full voltage of the vi domains on the whole board is 9.6V-nine.9V

1.3 S9K S9SE clock is composed of two 25M active crystal oscillators (Y1, Y2), Y1 is transmitted from the first bit to the 30th chip in serial, and Y2 is transmitted from the 31st chip to the 60th chip in series

1.4 At that place is independent minor cooling fin on the front and back of each chip of the S9K S9SE hash lath. The pocket-size cooling fin on the front side is the SMT patch, and the small cooling fin on the back side is fixed on the dorsum of the IC by the thermally conductive adhesive afterward the initial measurement. After the repaired and replaced flake passes the test, it is necessary to evenly use black thermally conductive adhesive on the IC surface and heat and fix it.

Note:

In the maintenance procedure, when replacing the circuit lath components or the bit, in order to reduce the damage of high temperature of the blower gun to the PCB board and the chip, it is necessary to first remove the pocket-size cooling fins most the faulty component and on the dorsum of the PCB lath earlier replacing.

There are test points on the PCB fleck surfaces. When manufacturing and repairing, if there is no cooling fin attached on the PCB bit, the test point on the chip surface can be used; for repair of finished products (afterward-sales repair), since the front end and back of the PCB are covered by cooling fins, information technology needs to locate fault through the exam betoken on the chip surface of the PCB. A special slender test pb can be used to probe the cooling fin gap for measurement. However, since the SMT small cooling fin is continued to the ground of each voltage domain, it is necessary to pay attention to the insulation of the exam lead in measurement to avoid short circuit caused by the test atomic number 82.

2. Analysis of primal point

2.1 The post-obit figure shows the chip domain distribution, signal path and excursion distribution of the S9K S9SE signal board:

TMP451 temperature sense

The catamenia direction of CLKO signal is generated by Y1 25M crystal oscillator, which is transmitted from chip U1 to chip U30; information technology is generated by Y2 25M crystal oscillator, and is transmitted from chip U31 to chip U60. When standby and computing, the voltage is 0.9V.

Point CO (CI, C0) enters from the Pin 7 at port IO (J4), and is then transmitted from chip U1 to chip U60; when the IO line is not inserted, the voltage is 0, and the voltage is ane.8V when computing.

Signal RI (R1, RO) returns from fleck U60 to fleck U1, and and then returns to the control lath from the pivot (J4) 8 at IO port; when the IO signal is not inserted, the voltage is 1.8V, and the voltage is i.8V when computing.

Signal BO (BI, BO) flows from bit U1 to U60 to lower the level; the voltage is 0V when there is no IO line inserted and during standby, there is a pulse indicate around 0.3 when computing, generally if no voltage tin be measured, it is normal.

Signal NRSTO (NRSTO, NRSTI) enters from pivot (J4)) 3 at IO port, and is and so transmitted from chip U1 to chip U60; the voltage is 0V when there is no IO point inserted and during standby, and the voltage is 1.8V when computing.

2.2 Key circuits of the S9K S9SE hash board

2.2.1 Schematic diagram of U122 power management

2.2.2 Schematic diagram of DC to DC excursion

2.2.3 Schematic diagram of EEPROM IC (single board test volition change the magic number, temperature sensing information and CRC information in the EEPROM)

2.2.4 Schematic diagram of clamping circuit

two.2.5 Schematic diagram of Picture show U102

ii.2.vi Signal test points of each chip (every bit shown below after amplified):

one. Bespeak test points in Domain 1, 3, 5

ii. Bespeak exam points in Domain 2, 4, 6

2.2.7 Pivot circuit diagram of each chip in Domain 1, three, and v

2.2.8 Pin circuit diagram of each fleck in Domain 2, 4, and 6

2.ii.ix Excursion diagram of J4 at IO port

2.2.10 0.8V, 1.8V excursion schematic diagram

2.2.11 Schematic diagram for Level bespeak conversion

2.two.12 Schematic diagram for Y1, Y2 crystal oscillator

2.2.13 LDO 0.8V, ane.8V and crystal oscillator measurement

S9K S9SE maintenance ideas

During the maintenance, conduct 10 tests earlier and after the main examination fleck (5 before and after the fleck: CLKO, CO, RI, BO, NRSTO); DC-DC output and PIC voltage

Core voltage; LDO (0.8V 1.8V), PLL-0.8V.

Detection method:

1. When the IO line is not inserted and merely 12V is inserted: the DC-DC output is nearly 0V, and the boost output is about 0V. The PIC power supply of 3.3V must be powered. The other exam voltages are all 0;

2. When the IO line is inserted and the test push is not pressed, there is no voltage output from DC-DC and boost. Later pressing the test push, the Moving picture starts to piece of work. At this time, the DC-DC outputs the voltage fix by the test program of Pic jig, and boosts as information technology works. And then the jig outputs Work, and returns to noce after computing. At this point, the normal voltage of each test point should be:

CLKO: 0.9V

CO: 1.6-1.8V, when the jig is just sent to Work, since the CO is negative, the DC level will be lowered, and the instantaneous voltage is well-nigh 1.5V. RI: 1.6-1.8V, when the voltage is abnormal or besides depression during computing, the hash lath will exist abnormal or the hashrate will be nada.

BO: 0V when there is no calculating, there volition be a pulse jump between 0.1-0.3V during computing.

NRSTO: 1.8V. A reset signal is re-outputted each time the examination push button of the jig is pressed.

When the above-mentioned test point status or voltage is abnormal, please estimate the fault signal based on the excursion earlier and after the test point.

Details and stardom of S9K S9SE chip'due south configuration file

PCBA characterization diagram

Clarification of chip correspondence

Four. Routine Maintenance Process

1. Routine testing: First acquit out visual inspection of the hash board to be repaired to come across if there is displacement, deformation, burning of small-scale cooling fin? If at that place is such phenomenon, it has to be processed kickoff; if the small cooling fin is displaced, remove it first and and so clear the black agglutinative, and then re-agglutinative after repair.

Secondly, after it's confirmed no trouble visual inspection, the impedance of each voltage domain can be detected first to notice whether there is a short circuit or an open up circuit. If found, it must be handled get-go.

Adjacent, check whether the voltages in each voltage domain reach 1.6v, and the voltage difference between the voltage domains must non exceed 0.3V. If the voltage in a voltage domain is too high or too low, the circuits in the adjacent voltage domain generally accept aberrant phenomena, and information technology needs to discover the reason first.

2. Later on confirming there is no problem in the routine test (short excursion detection is necessary in routine test to avoid burning the chip or other materials due to short circuit when it's power-on), a test box can be used for flake detection, and the detection results of the test box can be used to judge the location.

3. Co-ordinate to the event of the test box detection, start from the vicinity of the faulty flake, and discover the voltage of the fleck test point (CLK IN OUT/RI IN OUT/CO IN OUT/BO IN OUT/NRST IN OUT) and LDO 0V8 1V8.

4. Co-ordinate to the signal flow direction, the RI signal is reversely transmitted (U60 to U1 chip), and several of the signals CLK CO BO NRST are transmitted forward (U1-U60), and an abnormal fault signal is plant through the power supply sequence.

5. When locating to the faulty chip, the chip needs to exist rewelded. The method is to add together a flux around the scrap (preferably no-make clean flux), rut the solder joints of the scrap pins to a dissolved country, gently motility upward and down, left and right, and press the bit; promote the chip pins to joint the bonding pad again, collect the tin, then as to can again. If the fault is the same after re-welding, the bit can be replaced directly.

6. After the repair of the hash board, the test box must be checked for more than twice. The time of the two tests: For the get-go time, subsequently replacing the parts, the hash board needs to be cooled downwards; after passing the exam, it is put aside first. For the second time, after the hash board is completely cooled subsequently a few minutes, the examination is performed. Although each of the 2 tests lasts but a few minutes, it does not touch the piece of work. The repaired board is put bated, and the second lath is repaired, after the second board is repaired, it is placed and cooled, then the first board is tested. In manner, the repair is staggered and at that place is no delay in the full length of time.

7. For the repaired board, first it is necessary to classify the faults and tape the replaced part model, location, and cause, to feed back to product, later on- sales, inquiry and development.

viii. Later on recording, install the whole miner for normal aging.

V. Fault Type

Mutual fault types of the S9K S9SE hash board:

1. Cooling fin falls, shifts and deforms

The cooling fin on the PCB lath on the back of the hash board chip is non allowed to shift or collide before power on, particularly the cooling fin with dissimilar voltages. The contact of the cooling fins in dissimilar voltage domains means that in that location is a possibility of short circuit at different voltage points.

Moreover, determine that each of the cooling fin on the hash board has good heat conduction and is firmly fixed.

When replacing or re-installing the cooling fin, clean the remainder adhesive on the cooling fin and chip and and then coat again. The residue thermally conductive agglutinative can be cleaned with absolute alcohol.

2. Impedance imbalance in each voltage domain

When the impedance of some voltage domains deviates from the normal value, it indicates that there are open and curt circuits in the abnormal voltage domain. Generally the chip is the most likely to crusade information technology. But there are three fries in each voltage domain, and often only one has problem when fault occurs. The method of finding the problem fleck can detect and compare the ground impedance of test points of each chip to find the aberrant point.

If there is a short circuit, first remove the cooling fin on the same voltage chip, then observe whether the flake pin's tin can is connected.

If a curt-excursion point cannot be found on the appearance, search the short-circuit point according to the resistance method or current cut-off method.

3. Voltage imbalance in voltage domain

When the voltage in some voltage domains is as well loftier or too low, there is commonly an abnormal IO signal in the abnormal voltage domain or adjacent voltage domain, which causes the next voltage domain to work abnormally and the voltage to exist unbalanced. The abnormal point can be found by detecting the point and voltage of each examination point, and some need to notice the abnormal signal by comparing the impedance of each test signal.

Notation that the CLK bespeak and the NRST signal are the two most probable to cause a voltage imbalance.

4. Lack of chips

The lack of fries means when the test box is beingness checked, not all of the 60 chips are detected, and often non all the fries are actually detected. The really lost (undetected) abnormal fries are not in the displayed position. At this time, information technology is necessary to accurately locate the aberrant fleck through testing.

The locating method tin can employ the RI cutoff method to notice the location of the aberrant chip. That is, footing the RI point of a flake, for case, after the RI output of the 50th chip is grounded in the voltage domain, theoretically, if all the chips in the front are normal, the test box should display that 50 chips are detected. If not all 50 chips are detected, information technology means that the abnormality is before the 50th bit; if fifty chips are detected, it means that the abnormal chip is after the 50th chip. Utilize this dichotomy to find out where the abnormal chip is located.

five. Cleaved chain

A cleaved concatenation is like to lack of chips, but in a broken chain, non all chips that cannot exist found are abnormal, but all the chips afterwards the aberrant chip are invalid due to a certain flake abnormality. For example, a flake itself can work, but it volition not forward other scrap data; at this fourth dimension, the entire signal

chain will come to an abrupt end, and lose a large part of it, which is called broken concatenation.

The broken chain port data can be displayed. For example, when the test box detects the chips, only xxx chips are detected. If the number of preset chips is non detected in the test box, information technology will not run, so it volition merely display how many chips are detected, at this time, according to the displayed number "30", the problem can be found past detecting the voltage and impedance of each test point earlier and after the 30th chip.

vi. No running

No running means that the examination box cannot detect the chip data of the hash board, simply displays NO hash board; this phenomenon is the most common and the fault range involved is besides wide.

1) No running caused by abnormal voltage in a certain voltage domain; the problem can be found by measuring the voltage in each voltage domain.

ii) A scrap aberration causes an aberration that tin can be found by measuring each test point signal.

CLK signal: 0.9V; the signal is output from flake U1 scrap to chip U60. In the current version, there are only ii crystal oscillators, Y1 is transmitted from the first chip to the 30th chip, and Y2 is transmitted from the 31st chip to the 60th bit, and the CLKO signal is abnormally searched according to the direction of signal transmission.

CO indicate: i.8V; this signal is transmitted through chips U1, U2,,,,, U60, when a sure bespeak in the binary method is abnormal, it can be detected frontward.

RI indicate: ane.8V; this signal is returned from chips U60,,,,,, U2, U1, confirm the crusade of the fault through the flake indicate tendency; when S9K S9SE hash board does non run, the signal is the highest priority, kickoff search for this signal.

BO signal: 0V, this signal can be lowered to high level when the scrap detects that the RI return indicate is normal, otherwise it is loftier level.

NRST signal: 1.8V; afterward the hash board is powered and the IO indicate is inserted, the signal is transmitted from U1, U2,,,,, and U60 to the last chip.

iii) LDO 0.8V, ane.8V abnormality maintenance

The normal value of the ground impedance of the LDO 0.8V IC output is 50-100 Ώ, and the normal impedance of the LDO ane.8V IC output is 0.9KΏ.

There are six LDO i.8V single hash boards and twelve LDOs 0.8V (for example, the power supply of domain i U1-U10 is U61 LDO one.8V , the power supply of U1-U5 is 0.8V U117, and the power supply of U6-U10 is 0.8V U79), Since the LDO is operated in series, the LDO ground short-circuit can be repaired by using the 2-fifth method. First, take the middle fleck, remove them one by 1, and find the problem chip to replace it;

4) Single lath Patter NG repair

Series port impress log (logo data), unmarried-chip and whole-chip hash board none recovery rate needs to reach 98%, if noce response rate is lower than 98%, report Patter NG; according to serial port print log, give priority to the replacement of the bit with the lowest single chip noce recovery rate;

5) The whole miner J: 4 maintenance

ane. J: four does not store the temperature sensing flake position, and needs to test with the test jig once, the temperature sending information is written into the EEPROM chip IC through the unmarried board test jig;

two. The single lath jig configuration file is wrong (the flake of the hash board, the BIN level does not match the jig configuration file), resulting in the whole miner reporting J: four;

Six. Maintenance Instructions

i. During maintenance, the maintenance personnel must be familiar with the part and menstruation direction of each examination point, the normal voltage value and the impedance value to footing.

2. Must exist familiar with the bit soldering, and so as not to cause PCB foaming deformation or pin harm.

3. BM1393 chip package, sixteen pins on both sides of the fleck. The polarity and coordinates must be aligned during soldering and must not exist misaligned.

4. When replacing the chip, the thermally conductive fixing adhesive around the bit must be cleaned to avoid secondary damage of the fleck caused by hanging or poor heat dissipation during IC soldering.

● Note:

1. Since the cooling fin on the back of the fleck is continued to the flake, a special slender test lead must be used to detect the test point signal; autonomously from the metal exposed at the contact end, the other parts of the test atomic number 82 must exist sealed with a rut shrinkable tube so as to prevent the exam lead from contacting with the cooling fin and the test point at the same fourth dimension. In item, the voltage difference betwixt the upper and lower rows of excursion voltage is large, and will cause harm to the chip when contacting the basis (cooling fin) and test points in dissimilar voltage domains, and special attention shall exist paid.

two. In soldering, since there are pocket-size cooling gins close to the PCB on the dorsum of the chip, the rut conduction is fast. Therefore, it is necessary to use the bottom to help heating (nigh 200 degrees) in soldering, which can ameliorate the efficiency and reduce the damage to the PCB board. If there is no bottom heating device, remove the small cooling fin on the PCB on the dorsum of the scrap earlier replacing the fleck.

Delight contact our engineering department in time for new fault types. Nosotros will clarify and update this content continuously!

Source: https://ru.zeusbtc.com/manuals/Antminer-S9K-S9SE-Hash-Board-Repair-Guide.asp

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